The present invention is directed to electronic devices and, more particularly, to repairable electronic devices that include redundant regions for replacing defective regions of the device, such as the cells of a semiconductor memory device.
Semiconductor memory devices, such as dynamic random access memory devices (DRAMs), typically include a semiconductor memory cell array formed of a plurality of memory cells arranged in rows and columns and include a plurality of bit lines as well as a plurality of word lines that intersect the bit lines. Each memory cell of the array is located at the intersection of a respective word line and a respective bit line and includes a capacitor for storing data and a transistor for switching, such as a planar or vertical MOS transistor. The word line is connected to the gate of the switching transistor, and the bit line is connected to the source or drain of the switching transistor. When the transistor of the memory cell is switched on by a signal on the word line, a data signal is transferred from the capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the capacitor of the memory cell.
As the capacity of semiconductor memory devices increases, the likelihood that a device includes one or more defective memory cells also increases, thereby adversely affecting the yield of the semiconductor memory device manufacturing processes. To address this problem, redundant memory cells are provided which can replace memory cells that are found to be defective during device testing. Typically, one or more spare rows, known as row redundancy, and/or one or more spare columns, known as column redundancy, are included in the memory cell array. The spare rows and/or columns have programmable decoders that can be programmed to respond to the address of the defective row and/or column, known as the fail address, while at the same time disabling the selection of the defective cell. To program the address of a defective memory cell into the programmable decoder, one or more fuses are programmed to represent the respective bits of the fail address by blowing selected ones of the fuses. One of a 0 or 1 value is defined as a fuse in a blown or open state, and the other of the 0 and 1 values is defined as a fuse in an unblown or shorted state.
When an address of a defective memory cell is received, the redundant memory cell is selected so that part or all of the word line or bit line that is connected to the redundant memory cell is substituted for the corresponding portion of a word line or bit line of entire word line or bit line that contains the defective memory cell. As a result, the repaired memory device chip cannot be readily distinguished, at least electrically, from a defect-free chip.
Though semiconductor device elements have become increasingly smaller as the minimum feature size of the device elements has decreased, the total area of the device chip may not significantly decrease because of the presence of other elements on the chip whose size cannot be reduced. As an example, the spacing of the programmable fuse elements described above cannot be reduced below a minimum value, typically 1 μm, because of the laser cutting used to “blow” the fuse elements. A minimum spot size is needed for the incident laser beam to deliver sufficient energy to blow the fuse. Though beams having smaller spot sizes are possible by reducing the wavelength of the beam, the energy of the beam is also reduced and may not be sufficient to ensure cutting of the fuse. Moreover, as the spot size approaches the wavelength of the beam, the beam is prone to diffraction so that the beam cannot be focused on the fuse element.
Another device element whose size and/or spacing cannot readily be reduced below a minimum size is the bonding pad. When wire bonds are used, the width of the bonding wires and the size of the solder connections cannot be shrunk without risking breakage of the bonding wires, inadequate solder for the connection or misaligned bonding connections. When the bonding pads directly contact the lead frame, such as for a flip chip device, a minimum spacing between leads is also required.
It is nevertheless desirable to reduce the total area of the chip despite the limitations of fuse size and spacing and bonding pad size and spacing.